Learning About Icarus Verilog
See also: Learning About FPGA, Learning About GtkWave
Introduction
At the moment this page is for my notes on learning both Icarus Verilog the toolset and Verilog the language.
Project One : "Lock"
This "lock" requires the correct order of input pin toggling to enable the output. Input in2 must first be asserted high; this must then be followed by in1 being asserted high to "unlock" the output.
To simulate the design and produce the wave output you need to execute this command line:
iverilog -olock_tb lock_tb.v lock.v && vvp lock_tb
It should produce this:
VCD info: dumpfile test.vcd opened for output. At time 0, 0, 0, 0 At time 2, 0, 1, 0 At time 4, 0, 0, 0 At time 5, 0, 0, 1 At time 7, 0, 0, 0 At time 12, 0, 0, 1 At time 14, 0, 0, 0 At time 15, 1, 1, 0 At time 17, 1, 0, 0 ** VVP Stop(0) ** ** Current simulation time is 27 ticks. ** Interactive mode not supported, exiting simulation.
(Yes, I realise it wouldn't take long to brute-force. :-p )