module lock(out, clk, reset, in1, in2);

  output out;
  input clk, reset;
  input in1, in2; // code input keys

  reg out;
  wire 	       clk, reset;
  wire in1, in2;

  reg [7:0]state = 0;

  always @(posedge clk)
    begin

    //out <= !out;
    if (state == 0) begin
      if (in2) begin
        state <= 1;
      end
      out <= 0;
    end else if (state == 1) begin
      if (in1) begin
        out <= 1;
        state <= 2;
      end else begin
        out <= 0;
        state <= 0;
      end
    end else if (state == 2) begin
      out <= 1;
    end else
      out <= 0;


/*
      if (state == 0) begin
        if (in2) begin
          out <= 1;
        end
      end
*/
    end

  always @reset
    if (reset) begin
      assign out = 0;
      assign state = 0;
    end else begin
      deassign out;
      deassign state; // ?
    end

endmodule // lock