module test;

initial
 begin
    $dumpfile("test.vcd");
    $dumpvars;
 end

  /* Make a regular pulsing clock. */
  reg clk = 0;
  always #1 clk = !clk;


  /* Make a reset that pulses once. */
  reg reset = 0;
  reg in1 = 0;
  reg in2 = 0;
  initial begin
     # 0 reset = 1;
     # 1 reset = 0;
     # 1 in1 = 1;
     # 2 in1 = 0;
     # 1 in2 = 1;
     # 2 in2 = 0;
     # 3 reset = 1;
     # 1 reset = 0;
     # 1 in2 = 1;
     # 2 in2 = 0;
     # 1 in1 = 1;
     # 2 in1 = 0;
     # 10 $stop;
  end

  wire outvalue;
  lock c1 (outvalue, clk, reset, in1, in2);

  initial
     $monitor("At time %t, %d, %d, %d", $time, outvalue, in1, in2);


endmodule // test